List of SNES hardware registers

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This is a list of all the hardware registers used by the SNES (including some enhancement chips) and what they are used for. This list is incomplete.

Contents

Native SNES registers

Register Register name/use Size (8/16-bit) Write (once/twice) Bits Usage
$2100 Screen Display 8-bit Write-once f---bbbb Bits 0-3: Screen brightness. 0000 is completely black, 1111 is maximum brightness.
Bits 4-6: Unused.
Bit 7: Force blank. Setting this bit will turn force blank on, which turns the screen display off.
$2101 Object Size and Chr Address 8-bit Write-once sssnnbbb Bits 0-2: Name base select.
Bits 3-4: Name select.
Bits 5-7: Object size.
  000: 8x8/16x16 sprites


SA-1 registers

Write registers

Register Register name/use Size (8/16-bit) Write/read from Bits Usage
$2200 SA-1 CPU Control (CCNT) 8-bit SNES CPU irsnmmmm Bit 7: IRQ bit; When set, interrupt the SA-1.

Bit 6: "Ready" bit (?).
Bit 5: Stop bit; When set, stop the SA-1; When unset, the SA-1 jumps to the location stored in the RESET vector.
Bit 4: NMI bit; When set, interrupt the SA-1.
Bits 0-3: Message to SA-1; Can be read by the SA-1 as bits 0-3 of $2301.
Initialized to $20, meaning this must be written before the SA-1 executes any code.

$2201 SNES CPU Interrupt enable (SIE) 8-bit SNES CPU i-c----- Bit 7: Enable IRQs from the SA-1 to the SNES.

Bit 5: Enable character conversion DMA IRQs from the SA-1 to the SNES.
Note that writing this register with these bits unset does not disable interrupts, use $2202 for that.

$2202 SNES CPU Interrupt disable (SIC) 8-bit SNES CPU i-c----- The bits here are the same as $2201, but they disable interrupts when set instead of enabling them.
$2203, $2204 SA-1 RESET Vector (CRV) 16-bit SNES CPU 16-bit address for the SA-1 to jump to on reset.
$2205, $2206 SA-1 NMI Vector (CNV) 16-bit SNES CPU 16-bit address for the SA-1 to jump to when sent NMI from the SNES.
$2207, $2208 SA-1 IRQ Vector (CIV) 16-bit SNES CPU 16-bit address for the SA-1 to jump to when sent IRQ.
$2209 SNES CPU Control (SCNT) 8-bit SA-1 CPU Ii-nmmmm Bit 7: If set, send IRQ to the SNES CPU.

Bit 6: When set, the SNES will use the address in $220E-$220F for IRQ instead of the normal address.
Bit 4: When set, the SNES will use the address in $220C-$220D for NMI instead of the normal address.
Bits 0-3: Message to the SNES; can be read by the SNES as bits 0-3 of $2300.

$220A SA-1 CPU Interrupt Enable (CIE) 8-bit SA-1 CPU itdn---- Bit 7: If set, enable SNES -> SA-1 IRQ.

Bit 6: If set, enable IRQ from SA-1 timer to SA-1 CPU.
Bit 5: enable IRQ to SA-1 when the SA-1 has completed DMA.
Bit 4: when set, enable SNES -> SA-1 NMI.
Writing this register with these bits unset will not disable interrupts, use $220B for that.

$220B SA-1 CPU Interrupt Disable (CIC) 8-bit SA-1 CPU itdn---- The bits here are the same as $220A, except they disable interrupts when set instead of enabling them.
$220C, $220D SNES Special NMI Vector (SNV) 16-bit SA-1 CPU 16-bit address for the SNES to jump to when NMI occurs and bit 4 of $2209 is set.
$220E, $220F SNES Special IRQ Vector (SIV) 16-bit SA-1 CPU 16-bit address for the SNES to jump to when IRQ occurs and bit 6 of $2209 is set.
$2210 SA-1 Timer Control (TMC) 8-bit SA-1 CPU l-----vh Bit 7: If set, the SA-1 timer will be linear instead of H/V.

Bit 1: Base IRQ signal timing on vertical count.
Bit 0: Base IRQ signal timing on horizontal count.

$2211 SA-1 Timer Reset (CTR) 8-bit SA-1 CPU Writing any value to this restarts the SA-1 timer at zero.
$2212, $2213 SA-1 H Timer Set (HCNT) 16-bit SA-1 CPU Under H/V timer, this sets the SA-1 timer's horizontal count. Value range is between between $0000-$0154. Under linear timer, the value is the low nine bits of the counter ($000-$1FF)
$2214, $2215 SA-1 V Timer Set (VCNT) 16-bit SA-1 CPU Under H/V timer, this sets the SA-1 timer's vertical count. Value range is between between $0000-$0105 in NTSC, and $0000-$0137 in PAL. Under linear timer, the value is the high nine bits of the counter ($000-$1FF)
$2224 SNES CPU BW-RAM Mapping (BMAPS) 8-bit SNES CPU 000bbbbb This controls the section of BW-RAM that will be mapped to $6000-$7FFF of bank $00-$3F and $80-$BF, from the SNES CPU perspective. Writing $00 maps $400000-$401FFF, writing $01 maps $402000-$403FFFF, and so on.
$2225 SA-1 CPU BW-RAM Mapping (BMAP) 8-bit SA-1 CPU sbbbbbbb This controls the section of BW-RAM that will be mapped to $6000-$7FFF of bank $00-$3F and $80-$BF, from the SA-1 CPU perspective.
Bit 7: Source section control. If unset, this register follows the same logic as $2224. If set, this, this register uses the BW-RAM in banks $60-$6F (the bitmap area) but uses ostensibly the same logic, aside from being 2 bits longer.
$2250 SA-1 Arithmetic Control (MCNT) 8-bit SA-1 CPU Decides the SA-1's math operator type. 0 is multiplication, 1 is division, 2 is cumulative sum. During cumulative sum, writing 2 here clears the results.
$2251, $2252 SA-1 Multiplicand/Dividend (MA) 16-bit SA-1 CPU Signed value, to be multiplied/divided by the value $2253. It does not need to be reset between operations when multiplying, but it does need to be reset when dividing. Results can be read from $2306 after $2254 is written.
$2253, $2254 SA-1 Multiplier/Divisor (MB) 16-bit SA-1 CPU This register is signed when multiplying and unsigned when dividing. After writing this, results of math operations can be read from $2306.

Read registers

Register Register name/use Size (8/16-bit) Write/read from Bits Usage
$2300 SNES CPU Flag Read (SFR) 8-bit SNES CPU Iicnmmmm Bit 7: SA-1 -> SNES IRQ flag. Bit 6: When set, the SNES will use the address in $220E-$220F for IRQ instead of the normal address. Bit 5: Character conversion flag. Bit 4: When set, the SNES will use the address in $220C-$220D for IRQ instead of the normal address. Bits 0-3: Message from SA-1 to SNES; mirror bits 0-3 of $2209.
$2301 SA-1 CPU Flag Read (CFR) 8-bit SA-1 CPU itdnmmmm Bit 7: SNES -> SA-1 IRQ flag. Bit 6: Timer IRQ flag. Bit 5: DMA completion IRQ flag. Bit 4: SNES -> SA-1 NMI flag. Bits 0-3: Message from SNES to SA-1; mirror bits 0-3 of $2200.
$2306 SA-1 Math result (MR) 40-bit SA-1 CPU Results of mathematical operations. When multiplying, $2306-$2309 serve as the signed product. When dividing, $2306-$2307 act as the signed quotient, and $2308-$2309 act as the unsigned remainder. In cumulative arithmetic, the whole group serves as the signed cumulative sum.

GSU-1 (SuperFX) registers

To be filled in.

GSU-2 (SuperFX) registers

To be filled in.

DSP-1 registers

To be filled in.

DSP-2 registers

To be filled in.

DSP-3 registers

To be filled in.

DSP-4 registers

To be filled in.

CX4 registers

To be filled in.

MSU-1 registers

Write registers

Register Register name/use Size Bits Usage
$2000 Status port 8-bit darpvvvv

d=Data port busy. While this is set, you'll get only #$00 from $2001.
a=Audio port busy. While this is set, no sound is playing.
r=Audio repeat flag. Mirrors the flag in $2007.
p=Audio playing flag. Mirrors the flag in $2007.
vvvv=Version. Always 1.

$2001 Stream port 8-bit - Returns one byte from the data file.
$2002 Identification 48-bit - Returns "S-MSU1" (53 2D 4D 53 55 31).

Read registers

Register Register name/use Size Bits Usage
$2000 Data port 32-bit - Controls the position in the data file. Writing to $2003 sets the D bit in $2000 for a while.
$2004 Audio track 16-bit - Sets the current audio track and stops playback if a previous track was playing. Writing to $2005 sets the A bit in $2000 for a while.
$2006 Audio volume 8-bit - Sets the volume for audio playback (linear scale: 0 = 0%, 255 = 100%).
$2007 Audio state 8-bit 000000rp

r=Audio repeat flag. Mirrored to $2000.
p=Audio playing flag. Mirrored to $2000.
Writes have no effect if the A bit of $2000 is set.

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